1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly to a semiconductor device with a dielectric layer and a semiconductor layer stacked on a surface of a semiconductor substrate, a semiconductor element formed in the semiconductor layer and a trench isolation region formed around the semiconductor element, and to a method of manufacturing the same.
2. Description of the Related Art
Conventionally, an HVIC (High Voltage IC) is known, which uses a dielectric isolation substrate with a dielectric layer and a semiconductor layer stacked on a surface of a semiconductor substrate, having an IC and a high withstand-voltage device formed monolithically on the surface of the semiconductor layer. The HVIC has advantages such as that devices being mounted can be isolated from each other, products for in-vehicle applications are expected to be developed owing to stable operation under a high temperature, and that a high withstand-voltage device can be fabricated utilizing the RESURF (Reduced Surface) effect.
For example, using the HVIC enables it to make a three-phase level shift circuit into a one-chip formation including even an output device. If a P channel device and an N channel device can be combined as a level shift device, a control circuit can be simplified. Therefore, with regards to the HVIC, it is an important issue to improve the property of the P channel device (particularly a P channel MOS transistor).
A high withstand-voltage P channel MOS transistor may have a source electrode of a predetermined length formed in the surface of a semiconductor layer, a ring-shaped gate electrode formed surrounding the source electrode, a ring-shaped drain electrode formed surrounding the gate electrode, and a ring-shaped trench isolation region formed surrounding the drain electrode.
Another high withstand-voltage P channel MOS transistor may have a drain electrode of a predetermined length formed in the surface of a semiconductor layer, a ring-shaped gate electrode formed surrounding the drain electrode, a ring-shaped source electrode formed surrounding the gate electrode, and a ring-shaped trench isolation region formed surrounding the source electrode (see for example Japanese Patent Laying-Open Nos. 11-312805 and 08-306893).
However, in the P channel MOS transistor with the source electrode arranged in the center section of the ring-shaped drain electrode, the circumference of the source electrode is shorter than the circumference of the drain electrode, resulting in a problem of a smaller amount of injected holes and a low current drivability. Although it is possible to enhance the current drivability by extending the circumference of each electrode, the device area will then be increased to go against the effort to reduce the area by integration.
Moreover, in the P channel MOS transistor with the drain electrode arranged in the center section of the ring-shaped source electrode, the equipotential distribution curves in the trench isolation region and an buried oxide film are high in density when a positive high potential is applied to the source electrode, resulting in a problem of a low withstand voltage.